The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 09, 2019

Filed:

Mar. 08, 2018
Applicant:

Semiconductor Energy Laboratory Co., Ltd., Atsugi-shi, Kanagawa-ken, JP;

Inventors:

Shunpei Yamazaki, Setagaya, JP;

Kengo Akimoto, Atsugi, JP;

Shigeki Komori, Isehara, JP;

Hideki Uochi, Atsugi, JP;

Tomoya Futamura, Atsugi, JP;

Takahiro Kasahara, Atsugi, JP;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G02F 1/1362 (2006.01); H01L 27/02 (2006.01); H01L 27/12 (2006.01); H01L 33/00 (2010.01);
U.S. Cl.
CPC ...
G02F 1/136204 (2013.01); H01L 27/0248 (2013.01); H01L 27/124 (2013.01); H01L 27/1225 (2013.01); H01L 33/0041 (2013.01); H01L 2924/0002 (2013.01);
Abstract

In order to take advantage of the properties of a display device including an oxide semiconductor, a protective circuit and the like having appropriate structures and a small occupied area are necessary. The protective circuit is formed using a non-linear element which includes a gate insulating film covering a gate electrode; a first oxide semiconductor layer over the gate insulating film; a channel protective layer covering a region which overlaps with a channel formation region of the first oxide semiconductor layer; and a first wiring layer and a second wiring layer each of which is formed by stacking a conductive layer and a second oxide semiconductor layer and over the first oxide semiconductor layer. The gate electrode is connected to a scan line or a signal line, the first wiring layer or the second wiring layer is directly connected to the gate electrode.


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