The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 09, 2019
Filed:
Nov. 07, 2016
Boe Technology Group Co., Ltd, Beijing, CN;
Beijing Boe Display Technology Co., Ltd., Beijing, CN;
Jinhu Cao, Beijing, CN;
Minghui Ma, Beijing, CN;
Jiaxin Yu, Beijing, CN;
Fengwu Yu, Beijing, CN;
Bin Cao, Beijing, CN;
Namin Kwon, Beijing, CN;
Wei Li, Beijing, CN;
Zhi Li, Beijing, CN;
Xinlei Cao, Beijing, CN;
Enke Guo, Beijing, CN;
BOE TECHNOLOGY GROUP CO., LTD, Beijing, CN;
BEIJING BOE DISPLAY TECHNOLOGY CO., LTD., Beijing, CN;
Abstract
In some embodiments, an array substrate motherboard and a fabricating method thereof are provided. The method includes: providing a substrate including multiple gate lines, gate driving leads, data lines, and data driving leads, each gate line corresponds to one gate driving lead, each data line corresponds to one data driving lead; forming multiple gate line testing leads, each gate line testing lead is connected with a gate driving lead; forming multiple data line testing leads, each data line testing lead is connected with a subset of the multiple data driving leads; forming multiple gate line testing pads, each gate line testing pad is connected with a gate line testing lead; forming multiple data line testing pads, each data line testing pad is connected with two data line testing leads; and using the gate line testing pads and gate line testing pads to test the gate lines and data lines.