The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 02, 2019

Filed:

Oct. 12, 2017
Applicant:

Denso Corporation, Kariya, Aichi-pref., JP;

Inventor:

Kazutaka Honda, Kariya, JP;

Assignee:

DENSO CORPORATION, Kariya, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 19/04 (2006.01); H03F 3/45 (2006.01); G01R 1/20 (2006.01); G01R 19/00 (2006.01); H03K 5/08 (2006.01); H03K 17/00 (2006.01);
U.S. Cl.
CPC ...
H03F 3/45179 (2013.01); G01R 1/20 (2013.01); G01R 19/0053 (2013.01); G01R 19/0084 (2013.01); G01R 19/04 (2013.01); H03F 3/45475 (2013.01); H03K 5/08 (2013.01); H03K 17/002 (2013.01); H03F 2203/45514 (2013.01); H03F 2203/45551 (2013.01);
Abstract

A voltage detection circuit includes two detection capacitors, which are paired and configured differentially, first to third detection switches, a drive part, a minimum selector and a maximum selector. The first detection switch is formed of a pMOS transistor, which opens and closes a path between one of the detection capacitors and an input node. The second detection switch is formed of an nMOS transistor, which opens and closes a path between the other of the detection capacitors and an input node. The third detection switch is formed of a series circuit of a pMOS transistor and an nMOS transistor, which open and close a path between two detection capacitors. The driving part turns on and off complementarily between the first and second switches and the third detection switch. The minimum selector applies a lower one of voltages of the input nodes as a substrate potential of the nMOS transistor. The maximum selector applies a higher one of the voltages of the input nodes as a substrate potential of the pMOS transistor.


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