The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 02, 2019

Filed:

Sep. 06, 2017
Applicant:

Avago Technologies International Sales Pte. Limited., Singapore, SG;

Inventors:

Valentina Della Torre, Irvine, CA (US);

Seema B. Anand, Rancho Palos Verdes, CA (US);

Howard Chi, Palo Alto, CA (US);

Matteo Conta, Irvine, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04B 1/06 (2006.01); H03F 1/26 (2006.01); H03F 1/56 (2006.01); H03F 3/19 (2006.01); H03F 3/24 (2006.01); H04B 1/10 (2006.01); H04B 1/40 (2015.01); H04L 27/00 (2006.01); H04B 1/04 (2006.01); H03F 1/22 (2006.01); H03F 3/26 (2006.01); H03K 21/08 (2006.01);
U.S. Cl.
CPC ...
H03F 1/26 (2013.01); H03F 1/223 (2013.01); H03F 1/56 (2013.01); H03F 3/19 (2013.01); H03F 3/245 (2013.01); H03F 3/265 (2013.01); H04B 1/04 (2013.01); H04B 1/10 (2013.01); H04B 1/40 (2013.01); H04L 27/0002 (2013.01); H03F 2200/294 (2013.01); H03F 2200/333 (2013.01); H03F 2200/387 (2013.01); H03F 2200/451 (2013.01); H03K 21/08 (2013.01); H04B 2001/0491 (2013.01);
Abstract

The present disclosure is directed to a dual output path LNA that can be used to break the tradeoff between the output impedance and linearity of an LNA without the problems of a programmable output impedance LNA. In an embodiment, the dual output path architecture includes an LNA driving a low level of impedance in a low voltage gain path, thus achieving high linearity in the presence of large blockers, and driving a high level of impedance in a high voltage gain path to increase the LNA's voltage gain and minimize performance degradation due to a noisier, low power receiver front-end chain following the LNA. The present disclosure is further directed to a local oscillator (LO) offset circuit with low power and reduced spur generation.


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