The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 02, 2019

Filed:

Apr. 23, 2015
Applicant:

Seoul Viosys Co., Ltd., Ansan-si, KR;

Inventors:

Chang Yeon Kim, Ansan-si, KR;

Da Hye Kim, Ansan-si, KR;

Hong Chul Lim, Ansan-si, KR;

Joon Hee Lee, Ansan-si, KR;

Jong Kyun You, Ansan-si, KR;

Assignee:

Seoul Viosys Co., Ltd., Ansan-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 33/38 (2010.01); H01L 33/46 (2010.01); H01L 33/20 (2010.01); H01L 33/32 (2010.01); H01L 33/40 (2010.01); H01L 33/00 (2010.01); H01L 33/22 (2010.01);
U.S. Cl.
CPC ...
H01L 33/382 (2013.01); H01L 33/20 (2013.01); H01L 33/32 (2013.01); H01L 33/38 (2013.01); H01L 33/40 (2013.01); H01L 33/405 (2013.01); H01L 33/46 (2013.01); H01L 33/007 (2013.01); H01L 33/0079 (2013.01); H01L 33/22 (2013.01); H01L 2224/48463 (2013.01); H01L 2224/73265 (2013.01);
Abstract

Exemplary embodiments of the present invention relate to a high-efficiency light emitting diode (LED). The LED according to an exemplary embodiment includes a substrate, a semiconductor stack arranged on the substrate, wherein the semiconductor stack has a p-type semiconductor layer, an active layer and an n-type semiconductor layer, a first metal layer interposed between the substrate and the semiconductor stack, the first metal layer ohmic-contacted with the semiconductor stack, a first electrode pad arranged on the semiconductor stack, an electrode extension extending from the first electrode pad, wherein the electrode extension has a contact region contacting the n-type semiconductor layer, a first insulating layer interposed between the substrate and the semiconductor stack, wherein the first insulating layer covers a surface region of the p-type semiconductor layer under the contact region of the electrode extension, and a second insulating layer interposed between the first electrode pad and the semiconductor stack.


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