The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 02, 2019

Filed:

Aug. 15, 2016
Applicant:

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Jian Min, Beijing, CN;

Xiaolong Li, Beijing, CN;

Zhengyin Xu, Beijing, CN;

Ping Song, Beijing, CN;

Youwei Wang, Beijing, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 29/66 (2006.01); H01L 21/28 (2006.01); H01L 21/3105 (2006.01); H01L 27/12 (2006.01); H01L 29/786 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66765 (2013.01); H01L 21/02532 (2013.01); H01L 21/02592 (2013.01); H01L 21/02675 (2013.01); H01L 21/28008 (2013.01); H01L 21/31053 (2013.01); H01L 27/1218 (2013.01); H01L 27/1229 (2013.01); H01L 27/1262 (2013.01); H01L 27/1296 (2013.01); H01L 29/42384 (2013.01); H01L 29/78618 (2013.01); H01L 29/78636 (2013.01); H01L 29/78678 (2013.01);
Abstract

The present disclosure provides a TFT, its manufacturing method, an array substrate and a display device. The method includes steps of: forming a pattern of a gate electrode on a base substrate; forming a gate insulation layer with an even surface; forming a pattern of a polysilicon semiconductor layer; and forming patterns of a source electrode and a drain electrode. The step of forming the pattern of the polysilicon semiconductor layer includes: crystallizing the amorphous silicon layer, so as to form the polysilicon semiconductor layer.


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