The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 02, 2019

Filed:

Sep. 20, 2017
Applicant:

Fujifilm Corporation, Tokyo, JP;

Inventor:

Yoshiki Maehara, Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/311 (2006.01); H01L 29/423 (2006.01); H01L 29/786 (2006.01); H01L 51/05 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66742 (2013.01); H01L 21/31105 (2013.01); H01L 29/42356 (2013.01); H01L 29/78696 (2013.01); H01L 51/0558 (2013.01);
Abstract

Provided are an air up type transistor which has high electrical connection reliability and high productivity, and is capable of exhibiting good transistor characteristics while achieving microfabrication, and a manufacturing method of a transistor. A semiconductor layer is formed on an upper surface of a support precursor layer which becomes a semiconductor layer support and then a part of the semiconductor layer is removed to form one or more opening portions from which the support precursor layer is exposed. Two etching protective layers are formed on the semiconductor layer such that the two etching protective layers are separated from each other and at least a part of the opening portion is positioned in a region between the two etching protective layers. A part of the support precursor layer is removed by bringing an etchant into contact with the support precursor layer through the plurality of opening portions, thereby forming a space at a position corresponding to a region between the two etching protective layers so as to form two semiconductor layer supports that are arranged with the space interposed therebetween.


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