The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 02, 2019

Filed:

Oct. 06, 2017
Applicant:

Renesas Electronics Corporation, Koutou-ku, Tokyo, JP;

Inventors:

Kosuke Yoshida, Kawasaki, JP;

Tetsuya Nitta, Kawasaki, JP;

Atsushi Sakai, Kawasaki, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 29/78 (2006.01); H01L 29/10 (2006.01); H01L 29/739 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0634 (2013.01); H01L 29/1095 (2013.01); H01L 29/7393 (2013.01); H01L 29/7813 (2013.01); H01L 29/7816 (2013.01);
Abstract

In a semiconductor device, a pback gate region (PBG) is arranged in a main surface (S) between first and second portions (P, P) of an nsource region (SR), and arranged on a side closer to an ndrain region (DR) with respect to the nsource region (SR). Thereby, a semiconductor device having a high on-state breakdown voltage can be obtained.


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