The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 02, 2019

Filed:

Mar. 15, 2017
Applicant:

Abb Schweiz Ag, Baden, CH;

Inventors:

Wolfgang Janisch, Unterkulm, CH;

Atze de Vries, Seengen, CH;

Sven Matthias, Lenzburg, CH;

Assignee:

ABB Schweiz AG, Baden, CH;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/22 (2006.01); H01L 21/225 (2006.01); H01L 21/20 (2006.01); H01L 29/66 (2006.01); H01L 29/739 (2006.01); H01L 21/762 (2006.01); H01L 29/744 (2006.01); H01L 21/283 (2006.01); H01L 21/673 (2006.01); H01L 29/08 (2006.01);
U.S. Cl.
CPC ...
H01L 21/225 (2013.01); H01L 21/2007 (2013.01); H01L 21/2256 (2013.01); H01L 21/283 (2013.01); H01L 21/673 (2013.01); H01L 21/76256 (2013.01); H01L 29/66333 (2013.01); H01L 29/66363 (2013.01); H01L 29/7395 (2013.01); H01L 29/744 (2013.01); H01L 21/2253 (2013.01); H01L 29/0834 (2013.01); H01L 29/0873 (2013.01);
Abstract

A method for manufacturing a vertical power semiconductor device is provided, wherein a first impurity is provided at the first main side of a semiconductor wafer. A first oxide layer is formed on the first main side of the wafer, wherein the first oxide layer is partially doped with a second impurity in such way that any first portion of the first oxide layer which is doped with the second impurity is spaced away from the semiconductor wafer by a second portion of the first oxide layer which is not doped with the second impurity and which is disposed between the first portion of the first oxide layer and the first main side of the semiconductor wafer. Thereafter a carrier wafer is bonded to the first oxide layer. During front-end-of-line processing on the second main side of the semiconductor wafer, the second impurity is diffused from the first oxide layer into the semiconductor wafer from its first main side by heat generated during the front-end-of-line processing.


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