The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 02, 2019

Filed:

Jan. 04, 2018
Applicant:

Stmicroelectronics S.r.l., Agrate Brianza, IT;

Inventors:

Giovanni Campardo, Bergamo, IT;

Salvatore Polizzi, Palermo, IT;

Assignee:

STMICROELECTRONICS S.R.L., Agrate Brianza, IT;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2006.01); G11C 16/26 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 7/12 (2006.01); G11C 7/18 (2006.01); G11C 16/24 (2006.01); G11C 16/28 (2006.01);
U.S. Cl.
CPC ...
G11C 16/26 (2013.01); G11C 7/12 (2013.01); G11C 7/18 (2013.01); G11C 16/0408 (2013.01); G11C 16/08 (2013.01); G11C 16/24 (2013.01); G11C 16/28 (2013.01); G11C 2207/002 (2013.01); G11C 2207/12 (2013.01);
Abstract

A circuit for reading a memory cell of a non-volatile memory device provided with a memory array with cells arranged in wordlines and bitlines, among which a first bitline, associated to the memory cell, and a second bitline, has: a first circuit branch associated to the first bitline and a second circuit branch associated to the second bitline, each with a local node, coupled to which is a first dividing capacitor, and a global node, coupled to which is a second dividing capacitor; a decoder stage for coupling the local node to the first or second bitlines and coupling the global node to the local node; and a differential comparator stage supplies an output signal indicative of the datum stored; and a control unit for controlling the decoder stage, the coupling stage, and the differential comparator stage for generation of the output signal.


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