The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 02, 2019

Filed:

Sep. 25, 2017
Applicant:

Toshiba Memory Corporation, Tokyo, JP;

Inventors:

Katsuya Ohno, Yokohama Kanagawa, JP;

Konosuke Watanabe, Kawasaki Kanagawa, JP;

Kenta Yasufuku, Yokohama Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/06 (2006.01); G06F 12/02 (2006.01); G11C 16/10 (2006.01); H03M 13/29 (2006.01); H03M 13/27 (2006.01); G06F 11/10 (2006.01); G06F 3/06 (2006.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0246 (2013.01); G06F 3/064 (2013.01); G06F 3/0619 (2013.01); G06F 3/0656 (2013.01); G06F 3/0688 (2013.01); G06F 11/108 (2013.01); G06F 11/1044 (2013.01); G06F 11/1072 (2013.01); G11C 16/10 (2013.01); H03M 13/27 (2013.01); H03M 13/2942 (2013.01); G11C 16/0483 (2013.01);
Abstract

A storage device that can be connected to a host device includes a plurality of nonvolatile memories. Each nonvolatile memory includes first memory cells connected to a first word line and second memory cells connected to a second word line. The second word line is adjacent to the first word line. A controller in the storage device is configured to maintain parity data in a memory area of the host device for the data that has been written to the first memory cells, and, upon detecting a failure in the writing of data to the second memory cells, restore the data written to the first memory cells using the parity data from the memory area of the host device.


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