The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 02, 2019

Filed:

Aug. 29, 2017
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Bharat Kumar Rangarajan, Bangalore, IN;

Rakesh Misra, Bangalore, IN;

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 12/08 (2016.01); G06F 1/32 (2019.01); G06F 12/02 (2006.01); G06F 1/3206 (2019.01); G06F 1/3234 (2019.01); G06F 11/36 (2006.01); H02H 3/32 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0238 (2013.01); G06F 1/3206 (2013.01); G06F 1/3234 (2013.01); G06F 3/0625 (2013.01); G06F 11/3656 (2013.01); H02H 3/32 (2013.01); G06F 2212/1028 (2013.01); G06F 2212/1032 (2013.01);
Abstract

In some aspects, a method for managing leakage power includes coupling a first supply rail to a cache memory if a processor is in a first performance mode, wherein the processor accesses the cache memory, and coupling a second supply rail to the cache memory if the processor is in a second performance mode. The method also includes detecting gating of a clock signal to the cache memory or the processor, and, upon detecting gating of the clock signal, switching the cache memory from the second supply rail to the first supply rail if the cache memory is currently coupled to the second supply rail.


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