The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 02, 2019
Filed:
Mar. 31, 2017
Applicant:
Fuji Electric Co., Ltd., Kawasaki-shi, JP;
Inventor:
Katsunori Suzuki, Matsumoto, JP;
Assignee:
FUJI ELECTRIC CO., LTD., Kawasaki-Shi, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
C30B 23/02 (2006.01); C30B 29/36 (2006.01); H01L 29/861 (2006.01); C30B 25/18 (2006.01); H01L 21/02 (2006.01); H01L 29/04 (2006.01); H01L 29/16 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
C30B 23/025 (2013.01); C30B 25/186 (2013.01); C30B 29/36 (2013.01); H01L 21/0243 (2013.01); H01L 21/02378 (2013.01); H01L 21/02433 (2013.01); H01L 21/02529 (2013.01); H01L 21/02634 (2013.01); H01L 21/02658 (2013.01); H01L 29/045 (2013.01); H01L 29/0619 (2013.01); H01L 29/1608 (2013.01); H01L 29/861 (2013.01); H01L 29/8613 (2013.01); H01L 29/6606 (2013.01);
Abstract
A semiconductor device is provided in which a front surface of an SiC substrate is treated before epitaxial growth so as to reduce crystal defects such as stacking faults. In an aspect, an epitaxial layer is deposited on an SiC substrate in which a periodic texture is formed in a direction perpendicular to a <−1100> direction of the SiC substrate and in which an angle between a basal plane of the SiC substrate and a surface of the formed texture is smaller than an off angle.