The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 26, 2019

Filed:

Feb. 21, 2017
Applicant:

Volkswagen Aktiengesellschaft, Wolfsburg, DE;

Inventors:

Olaf Krieger, Lostau, DE;

Lothar Claus, Koenigslutter, DE;

Christoph Hoffmann, Wolfsburg, DE;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 12/931 (2013.01); H04L 12/12 (2006.01); H04L 12/46 (2006.01); H04L 12/937 (2013.01); G06F 13/14 (2006.01); G06F 15/173 (2006.01); H04L 12/40 (2006.01);
U.S. Cl.
CPC ...
H04L 49/351 (2013.01); G06F 13/14 (2013.01); G06F 15/1735 (2013.01); G06F 15/17343 (2013.01); H04L 12/12 (2013.01); H04L 12/40 (2013.01); H04L 12/4625 (2013.01); H04L 49/253 (2013.01); G05B 2219/25012 (2013.01); G05B 2219/25174 (2013.01); Y02D 10/14 (2018.01); Y02D 50/40 (2018.01); Y02D 50/42 (2018.01);
Abstract

A switch unit for an Ethernet network having a switch and a microprocessor, the switch including at least three ports, which are connected to inputs and outputs of the switch unit, a signal detector and generator for detecting and initiating a bus activity being arranged in each case between the ports and the inputs and outputs of the switch unit. For each input and output an allocation rule to the other inputs and outputs of the switch unit is stored in a memory, the switch unit being designed such that when a bus activity is detected at a signal detector and generator, the assigned inputs and outputs of this input and output are read out from the memory and the associated signal detectors and generators are woken up so that they generate a bus activity at their inputs and outputs.


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