The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 26, 2019

Filed:

May. 25, 2017
Applicant:

Efficient Power Conversion Corporation, El Segundo, CA (US);

Inventors:

Michael A. de Rooij, Palm Springs, CA (US);

David C. Reusch, Blacksburg, VA (US);

Suvankar Biswas, Blacksburg, VA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/00 (2006.01); H03K 17/04 (2006.01); H01L 27/088 (2006.01); H01L 29/20 (2006.01); H03K 3/0233 (2006.01); H03K 19/0185 (2006.01); H03K 17/06 (2006.01); H03K 17/22 (2006.01); H01L 27/06 (2006.01);
U.S. Cl.
CPC ...
H03K 17/0406 (2013.01); H01L 27/088 (2013.01); H01L 29/2003 (2013.01); H03K 3/02337 (2013.01); H03K 17/063 (2013.01); H03K 17/223 (2013.01); H03K 19/018507 (2013.01); H01L 27/0605 (2013.01);
Abstract

A fully integrated GaN driver comprising a digital logic signal inverter, a level shifter circuit, a UVLO circuit, an output buffer stage, and (optionally) a FET to be driven, all integrated in a single package. The level shifter circuit converts a ground reference 0-5 V digital signal at the input to a 0-10 V digital signal at the output. The output drive circuitry includes a high side GaN FET that is inverted compared to the low side GaN FET. The inverted high side GaN FET allows switch operation, rather than a source follower topology, thus providing a digital voltage to control the main FET being driven by the circuit.


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