The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 26, 2019

Filed:

Aug. 19, 2016
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Brent A. Anderson, Jericho, VT (US);

Steven Bentley, Menands, NY (US);

Kwan-Yong Lim, Niskayuna, NY (US);

Hiroaki Niimi, Cohoes, NY (US);

Junli Wang, Slingerlands, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 29/423 (2006.01); H01L 27/088 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7827 (2013.01); H01L 21/823412 (2013.01); H01L 21/823487 (2013.01); H01L 27/088 (2013.01); H01L 29/4236 (2013.01); H01L 29/66636 (2013.01); H01L 29/66666 (2013.01); H01L 29/78 (2013.01); H01L 21/82345 (2013.01); H01L 21/823456 (2013.01);
Abstract

Embodiments of the present invention provide methods and systems for co-integrating a short-channel vertical transistor and a long-channel transistor. One method may include: from a starting substrate, forming a wide fin, wherein the wide fin comprises a wide active region; depositing a recess mask over a top surface of the starting substrate; recessing a long channel based on the deposited recess mask; depositing a gate electrode and a gate material, to form a gate structure; and forming SD contacts in an SD region of the long-channel transistor.


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