The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 26, 2019

Filed:

Dec. 11, 2014
Applicant:

Mitsubishi Electric Corporation, Tokyo, JP;

Inventors:

Kazuya Konishi, Tokyo, JP;

Yusuke Fukada, Tokyo, JP;

Atsushi Narazaki, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/739 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 21/762 (2006.01); H01L 21/761 (2006.01); H01L 21/265 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7397 (2013.01); H01L 21/26533 (2013.01); H01L 21/761 (2013.01); H01L 21/76224 (2013.01); H01L 29/0653 (2013.01); H01L 29/0696 (2013.01); H01L 29/1095 (2013.01); H01L 29/4236 (2013.01); H01L 29/4916 (2013.01); H01L 29/66348 (2013.01);
Abstract

A semiconductor device includes a first semiconductor layer on one main surface of a semiconductor substrate; a plurality of trench gates in the first semiconductor layer extending to reach the inside of the semiconductor substrate; a second semiconductor layer selectively provided in an upper portion of the first semiconductor layer between the trench gates; an isolation layer in contact with a side surface of the second semiconductor layer and extends in the first semiconductor; and a third semiconductor layer in the upper portion of the first semiconductor layer between the trench gates and has at least one side surface in contact with the trench gate. The isolation layer is between and separates the second semiconductor layer and the third semiconductor layer from each other and is formed to extend to the same depth as, or to a position deeper than the second semiconductor layer.


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