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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10243019 B1

PDFFull Text
Date of Patent:
Mar. 26, 2019

Filed:

Aug. 16, 2017

Electronic device and method for fabricating the same

Applicant:

SK Hynix Inc., Icheon-Si, KR;

Inventors:

Hyung-Suk Lee, Icheon-si, KR;

Do-Yeon Kim, Yongin-si, KR;

Assignee:

SK hynix Inc., Icheon-si, KR;

Attorney:

Perkins Coie LLP

Primary Examiner:

Fei Fei Yeung Lopez

Int. Cl.
CPC ...
H01L 27/22 (2006.01); H01L 43/02 (2006.01); H01L 43/08 (2006.01); H01L 43/12 (2006.01); H01L 45/00 (2006.01); H01L 41/297 (2013.01); H01L 41/27 (2013.01); H01L 41/20 (2006.01); H01L 41/22 (2013.01); H01L 41/12 (2006.01); G11C 13/00 (2006.01); H01L 27/24 (2006.01); G11C 11/16 (2006.01); H01L 43/10 (2006.01);
U.S. Cl.
CPC ...
H01L 27/222 (2013.01); G11C 13/0002 (2013.01); H01L 27/2409 (2013.01); H01L 41/12 (2013.01); H01L 41/20 (2013.01); H01L 41/22 (2013.01); H01L 41/27 (2013.01); H01L 41/297 (2013.01); H01L 43/02 (2013.01); H01L 43/08 (2013.01); H01L 43/12 (2013.01); H01L 45/1253 (2013.01); H01L 45/16 (2013.01); G11C 11/161 (2013.01); G11C 11/1673 (2013.01); G11C 11/1675 (2013.01); H01L 43/10 (2013.01);
Abstract

This technology provides an electronic device. An electronic device in accordance with an implementation of this document may include a semiconductor memory for storing data, and the semiconductor memory may include a substrate; an interlayer dielectric layer over the substrate and patterned to include a contact hole; a lower contact structure formed over the substrate in the contact hole; and a variable resistance element formed over and electrically coupled to the lower contact structure, wherein the lower contact structure may include: a spacer formed on sidewalls of the contact hole in the interlayer dielectric layer and having a substantially uniform thickness along a direction perpendicular to a surface of the substrate; a contact plug filling a portion of the contact hole; and a contact pad formed over the contact plug and filling a remaining portion of the contact hole.

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