The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 26, 2019

Filed:

Sep. 14, 2017
Applicant:

Sandisk Technologies Llc, Plano, TX (US);

Inventors:

Takashi Inomata, Yokkaichi, JP;

Nobuo Hironaga, Yokkaichi, JP;

Junichi Ariyoshi, Yokkaichi, JP;

Tadashi Nakamura, Yokkaichi, JP;

Assignee:

SANDISK TECHNOLOGIES LLC, Addison, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11524 (2017.01); H01L 27/11556 (2017.01); H01L 27/1157 (2017.01); H01L 27/11582 (2017.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 27/11565 (2017.01); H01L 27/11519 (2017.01); H01L 29/792 (2006.01); H01L 27/11575 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11556 (2013.01); H01L 21/76805 (2013.01); H01L 21/76816 (2013.01); H01L 21/76831 (2013.01); H01L 21/76877 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 27/1157 (2013.01); H01L 27/11524 (2013.01); H01L 27/11582 (2013.01); H01L 27/11519 (2013.01); H01L 27/11565 (2013.01); H01L 27/11575 (2013.01); H01L 29/7926 (2013.01);
Abstract

A monolithic three-dimensional memory device includes a first alternating stack of first insulating layers and first electrically conductive layers located over a top surface of a substrate, an insulating cap layer overlying the first alternating stack, a second alternating stack of second insulating layers and second electrically conductive layers and overlying the insulating cap layer, memory openings extending through the second alternating stack, the insulating cap layer, and the first alternating stack, memory stack structures located within the memory openings, and annular spacers located within the insulating cap layer and laterally surrounding a respective one of the memory stack structures.


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