The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 26, 2019
Filed:
Nov. 30, 2017
Method of forming a multilayer structure for reducing defects in semiconductor devices and structure
Semiconductor Components Industries, Llc, Phoenix, AZ (US);
SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Phoenix, AZ (US);
Abstract
A method of forming a semiconductor device includes providing a semiconductor substrate and forming amorphous semiconductor layers adjacent a major surface of the substrate. The method includes interposing dielectric layers between the amorphous semiconductor layers. The method includes forming polycrystalline semiconductor layers adjacent the amorphous semiconductor layers. The method includes interposing dielectric layers between the polycrystalline semiconductor layers and between the last amorphous semiconductor layer and the first polycrystalline semiconductor layer. The method includes forming a fine-grain polycrystalline semiconductor layer adjacent the polycrystalline semiconductor layers but is separated from the last polycrystalline semiconductor layer by an additional dielectric layer. The fine-grain polycrystalline semiconductor layer is formed at a higher temperature than the polycrystalline semiconductor layers and the amorphous semiconductor layers. A semiconductor device can be formed in another major surface of the semiconductor substrate.