The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 26, 2019
Filed:
Jan. 25, 2017
Applicant:
Microsoft Technology Licensing, Llc, Redmond, WA (US);
Inventors:
Tolga Ozguner, Redmond, WA (US);
Jeffrey Powers Bradford, Woodinville, WA (US);
Miguel Comparan, Kenmore, WA (US);
Gene Leung, Sammamish, WA (US);
Adam James Muff, Woodinville, WA (US);
Ryan Scott Haraden, Duvall, WA (US);
Christopher Jon Johnson, Snoqualmie, WA (US);
Assignee:
Microsoft Technology Licensing, LLC, Redmond, WA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G03H 1/00 (2006.01); G06F 3/01 (2006.01); G06T 1/20 (2006.01); G06T 1/60 (2006.01); G09G 3/00 (2006.01); G02B 27/01 (2006.01); G06F 12/02 (2006.01); G09G 5/395 (2006.01); G06F 12/121 (2016.01); G06F 12/128 (2016.01); G06F 12/0862 (2016.01);
U.S. Cl.
CPC ...
G09G 5/395 (2013.01); G02B 27/0103 (2013.01); G02B 27/017 (2013.01); G03H 1/0005 (2013.01); G06F 12/0862 (2013.01); G06F 12/121 (2013.01); G06T 1/20 (2013.01); G06T 1/60 (2013.01); G09G 3/003 (2013.01); G02B 2027/014 (2013.01); G02B 2027/0178 (2013.01); G02B 2027/0187 (2013.01); G03H 2001/0088 (2013.01); G06F 3/011 (2013.01); G06F 12/0207 (2013.01); G06F 12/128 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/1028 (2013.01); G06F 2212/1044 (2013.01); G06F 2212/455 (2013.01); G06F 2212/6026 (2013.01); G09G 2360/121 (2013.01);
Abstract
Systems and methods are disclosed herein for providing improved cache structures and methods that are optimally sized to support a predetermined range of late stage adjustments and in which image data is intelligently read out of DRAM and cached in such a way as to eliminate re-fetching of input image data from DRAM and minimize DRAM bandwidth and power.