The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 26, 2019

Filed:

Jul. 18, 2017
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

In-Jae Lee, Hwaseong-si, KR;

Kwang-Soo Kim, Hwaseong-si, KR;

Hyong-Woo Yu, Yongin-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/14 (2006.01); G06F 3/06 (2006.01); G06K 19/077 (2006.01); G11C 16/30 (2006.01); G06F 13/16 (2006.01); G06K 19/07 (2006.01); G11C 7/10 (2006.01); G11C 7/22 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0659 (2013.01); G06F 3/0604 (2013.01); G06F 3/0679 (2013.01); G06F 13/16 (2013.01); G06K 19/0712 (2013.01); G06K 19/07732 (2013.01); G06K 19/07743 (2013.01); G11C 16/30 (2013.01); G11C 7/1042 (2013.01); G11C 7/22 (2013.01); G11C 2207/2209 (2013.01);
Abstract

A memory card includes first and second groups of terminals, at least one controller, and first and second nonvolatile memories. The first group of terminals are adjacent to an edge at an insertion side of a substrate and include a first power terminal to provide a first voltage. The second group of terminals is spaced farther apart from the edge at the insertion side than the first group of terminals and includes a second power terminal to provide a second voltage. The at least one memory controller is connected to the first and second groups of terminals, and the first and second nonvolatile memories are independently connected to the at least one controller. The at least one controller simultaneously accesses the first nonvolatile memory and the second nonvolatile memory when the first group of terminals and the second group of terminals are connected to an external host.


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