The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 26, 2019

Filed:

Dec. 21, 2015
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-Do, KR;

Inventors:

Inseok Stephen Choi, Redwood City, CA (US);

Byoung Young Ahn, San Jose, CA (US);

Yang Seok Ki, Palo Alto, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/02 (2006.01); G06F 3/06 (2006.01); G06F 1/32 (2019.01); G06F 1/3234 (2019.01); G06F 1/3296 (2019.01); G11C 5/14 (2006.01); G11C 16/30 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0625 (2013.01); G06F 1/32 (2013.01); G06F 1/3275 (2013.01); G06F 1/3296 (2013.01); G06F 3/0659 (2013.01); G06F 3/0688 (2013.01); G11C 5/148 (2013.01); G11C 16/30 (2013.01); Y02B 60/1228 (2013.01); Y02B 60/1285 (2013.01); Y02D 10/14 (2018.01); Y02D 10/172 (2018.01);
Abstract

A solid state memory system includes: an interface circuit; a device processor, coupled to the interface circuit, configured to receive a dynamic power limit command through the interface circuit and update a metadata log based on the dynamic power limit command; a non-volatile memory array coupled to the interface circuit; and a power manager unit, coupled between the device processor and the non-volatile memory array, configured to alter an operating configuration of the non-volatile memory array to meet the requirement of the dynamic power limit command.


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