The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 26, 2019

Filed:

Dec. 12, 2013
Applicant:

Apple Inc., Cupertino, CA (US);

Inventors:

Conrado Blasco, Sunnyvale, CA (US);

Ronald P Hall, Austin, TX (US);

Ramesh B Gunna, San Jose, CA (US);

Ian D Kountanis, Santa Clara, CA (US);

Shyam Sundar, Sunnyvale, CA (US);

André Seznec, Acigné, FR;

Assignee:

Apple Inc., Cupertino, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/38 (2018.01); G06F 1/3237 (2019.01); G06F 1/324 (2019.01); G06F 1/3234 (2019.01); G06F 1/3296 (2019.01);
U.S. Cl.
CPC ...
G06F 1/3237 (2013.01); G06F 1/324 (2013.01); G06F 1/3275 (2013.01); G06F 1/3296 (2013.01); G06F 9/3802 (2013.01); G06F 9/3806 (2013.01); Y02D 10/126 (2018.01); Y02D 10/128 (2018.01); Y02D 10/14 (2018.01); Y02D 10/172 (2018.01);
Abstract

A processor includes a mechanism for disabling a memory array of a branch prediction unit. The processor may include a next fetch prediction unit that may include a number of entries. Each entry may correspond to a next instruction fetch group and may store an indication of whether or not the corresponding the next fetch group includes a conditional branch instruction. In response to an indication that the next fetch group does not include a conditional branch instruction, the fetch prediction unit may be configured to disable, in a next instruction execution cycle, the memory array of the branch prediction unit.


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