IDiyas

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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10237059 B1

PDFFull Text
Date of Patent:
Mar. 19, 2019

Filed:

Nov. 20, 2015

Diversified instruction set processing to enhance security

Applicants:

Lakshminarasimhan Sethumadhavan, New York, NY (US);

Kanad Sinha, New York, NY (US);

Angelos Keromytis, New York, NY (US);

Vasileios Pappas, New York, NY (US);

Vasileios Kemerlis, New York, NY (US);

Inventors:

Lakshminarasimhan Sethumadhavan, New York, NY (US);

Kanad Sinha, New York, NY (US);

Angelos Keromytis, New York, NY (US);

Vasileios Pappas, New York, NY (US);

Vasileios Kemerlis, New York, NY (US);

Assignee:

The Trustees of Columbia University in the City of New York, New York, NY (US);

Attorney:

Occhiuti & Rohlicek LLP

Primary Examiner:

Aravind Moorthy

Int. Cl.
CPC ...
G06F 12/14 (2006.01); H04L 29/06 (2006.01); H04L 9/08 (2006.01); H04L 9/00 (2006.01); H04L 9/28 (2006.01); G06F 21/72 (2013.01); G06F 9/30 (2018.01); G06F 12/0897 (2016.01); G06F 21/12 (2013.01); G06F 21/57 (2013.01);
U.S. Cl.
CPC ...
H04L 9/0825 (2013.01); G06F 9/30178 (2013.01); G06F 12/0897 (2013.01); G06F 12/1408 (2013.01); G06F 21/72 (2013.01); H04L 9/007 (2013.01); G06F 21/123 (2013.01); G06F 21/575 (2013.01); G06F 2212/1052 (2013.01);
Abstract

Disclosed are devices, systems, apparatus, methods, products, and other implementations, including a method that includes receiving a block of information from non-processor memory at an interface between the non-processor memory and processor memory comprising two or more processor memory levels, determining whether the block of information received from the non-processor memory at the interface corresponds to encrypted instruction code, and decrypting the block of information at the interface between the non-processor memory and the processor memory for storage in one of the two or more levels of the processor memory in response to a determination that the received block of information corresponds to the encrypted instruction code. The block of information is stored at the one of the two or more levels of the processor memory without being decrypted when the received block of information is determined to correspond to data.

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