The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 19, 2019

Filed:

Jun. 16, 2017
Applicant:

Semiconductor Energy Laboratory Co., Ltd., Atsugi-shi, Kanagawa-ken, JP;

Inventors:

Kazutaka Kuriki, Kanagawa, JP;

Mikio Yukawa, Kanagawa, JP;

Yuji Asano, Kanagawa, JP;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01M 4/38 (2006.01); H01M 12/08 (2006.01); H01M 10/0569 (2010.01); H01M 4/66 (2006.01); H01M 10/0525 (2010.01); H01G 11/06 (2013.01); H01G 11/28 (2013.01); H01G 11/30 (2013.01); H01G 11/46 (2013.01); H01G 11/50 (2013.01); H01L 49/02 (2006.01); H01G 11/26 (2013.01); H01M 4/04 (2006.01); H01M 4/134 (2010.01); H01M 4/1395 (2010.01); C30B 25/00 (2006.01); C30B 29/06 (2006.01); C30B 29/62 (2006.01); C30B 33/02 (2006.01); H01G 11/22 (2013.01); H01G 11/68 (2013.01); H01G 11/70 (2013.01); H01L 21/02 (2006.01); H01M 10/0583 (2010.01);
U.S. Cl.
CPC ...
H01M 4/386 (2013.01); C30B 25/005 (2013.01); C30B 29/06 (2013.01); C30B 29/62 (2013.01); C30B 33/02 (2013.01); H01G 11/06 (2013.01); H01G 11/22 (2013.01); H01G 11/26 (2013.01); H01G 11/28 (2013.01); H01G 11/30 (2013.01); H01G 11/46 (2013.01); H01G 11/50 (2013.01); H01G 11/68 (2013.01); H01G 11/70 (2013.01); H01L 28/82 (2013.01); H01M 4/0428 (2013.01); H01M 4/134 (2013.01); H01M 4/1395 (2013.01); H01M 4/382 (2013.01); H01M 4/661 (2013.01); H01M 4/667 (2013.01); H01M 10/0525 (2013.01); H01M 10/0569 (2013.01); H01M 12/08 (2013.01); H01L 21/0262 (2013.01); H01L 21/02532 (2013.01); H01L 21/02587 (2013.01); H01M 10/0583 (2013.01); H01M 2300/0037 (2013.01); Y02E 60/13 (2013.01); Y02P 70/54 (2015.11); Y02T 10/7011 (2013.01); Y02T 10/7022 (2013.01);
Abstract

Provided is a method for manufacturing a power storage device in which a crystalline silicon layer including a whisker-like crystalline silicon region is formed as an active material layer over a current collector by a low-pressure CVD method in which heating is performed using a deposition gas containing silicon. The power storage device includes the current collector, a mixed layer formed over the current collector, and the crystalline silicon layer functioning as the active material layer formed over the mixed layer. The crystalline silicon layer includes a crystalline silicon region and a whisker-like crystalline silicon region including a plurality of protrusions which project over the crystalline silicon region. With the protrusions, the surface area of the crystalline silicon layer functioning as the active material layer can be increased.


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