The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 19, 2019
Filed:
Sep. 15, 2015
Hitachi, Ltd., Chiyoda-ku, Tokyo, JP;
Yuki Mori, Tokyo, JP;
Akio Shima, Tokyo, JP;
Hitachi, Ltd., Tokyo, JP;
Abstract
An object of the present invention is to suppress energization deterioration due to crystal defects in a semiconductor device including SiC-MOSFET. To solve this problem, a semiconductor device of the present invention includes: an n-type epitaxial layer formed on a main surface of an n-type SiC substrate; a p-type termination region that is annularly formed in the n-type epitaxial layer outside an active region; and an n-type hole annihilation region annularly formed in the n-type epitaxial layer outside the p-type termination region, apart from the p-type termination region. Then, the n-type hole annihilation region has a first end surface facing the p-type termination region, as well as a second end surface on the opposite side of the first end surface. When a depth of the n-type hole annihilation region is d, a depth of the p-type termination region is d, a thickness of the n-type epitaxial layer is d, a distance from the first end surface of the n-type hole annihilation region to the second end surface thereof is L, and a distance from the first end surface of the n-type hole annihilation region to the periphery of the semiconductor substrate is |X|, these variables have the following relationship: d≤d, (|X|+d)≥d, 0<L<|X|.