The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 19, 2019

Filed:

Oct. 12, 2017
Applicant:

Avago Technologies International Sales Pte. Limited, Singapore, SG;

Inventors:

Qing Liu, Watervliet, NY (US);

Shom Ponoth, Irvine, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/13 (2006.01); H01L 29/417 (2006.01); H01L 49/02 (2006.01); H01L 27/06 (2006.01); H01L 27/12 (2006.01); H01L 29/786 (2006.01); H01L 21/768 (2006.01); H01L 23/485 (2006.01);
U.S. Cl.
CPC ...
H01L 29/41783 (2013.01); H01L 21/76895 (2013.01); H01L 23/485 (2013.01); H01L 27/0629 (2013.01); H01L 27/1203 (2013.01); H01L 27/13 (2013.01); H01L 28/20 (2013.01); H01L 29/78624 (2013.01);
Abstract

A three dimensional monolithic LDMOS transistor implements a drain structure vertically disposed above a level of the structure that includes a drain connection of the transistor. Displacing the drain structure vertically, out of the plane or level of the gate and source I drain connections, creates a three dimensional structure for the transistor. One result is that the transistor consumes far less lateral area on the substrate. The reduction in lateral area in turn provides benefits such as allowing transistors to be more densely arranged on the substrate and allowing additional devices of other types to be formed on the substrate.


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