The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 19, 2019

Filed:

Oct. 20, 2015
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Emre Alptekin, Fishkill, NY (US);

Hung H. Tran, Chicago, IL (US);

Reinaldo A. Vega, Wappingers Falls, NY (US);

Xiaobin Yuan, Carmel, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/06 (2006.01); H01L 29/739 (2006.01); H01L 29/78 (2006.01); H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0684 (2013.01); H01L 21/28114 (2013.01); H01L 29/66356 (2013.01); H01L 29/7391 (2013.01); H01L 29/78 (2013.01); H01L 21/28079 (2013.01); H01L 21/28088 (2013.01); H01L 21/28194 (2013.01);
Abstract

A tunnel field effect transistor (TFET) including a first doped source region for a first type TFET or a second doped source region for a second type TFET; a second doped drain region for the first type TFET or a first doped drain region for the second type TFET; a body region that is either intrinsic or doped, with a doping concentration less than that of the first or second source region, separating the first or second source from the first or second drain regions; a self-aligned etch cavity separating the first or second doped source and drain regions; a thin epitaxial channel region that is grown within the self-aligned etch cavity, covering at least the first or the second source region; a replacement gate stack comprising a high-k gate dielectric and one or a combination of metals and polysilicon; and sidewall spacers adjacent to the replacement gate stack.


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