The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 19, 2019

Filed:

Mar. 23, 2017
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-Do, KR;

Inventor:

Chang Ho Kim, Hwaseong-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-si, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/84 (2006.01); H01L 21/66 (2006.01); H01L 21/324 (2006.01); H01L 21/67 (2006.01);
U.S. Cl.
CPC ...
H01L 22/20 (2013.01); H01L 21/324 (2013.01); H01L 21/67115 (2013.01); H01L 21/67259 (2013.01); H01L 21/67288 (2013.01);
Abstract

An apparatus and a method for reducing wafer warpage are provided. The method includes positioning a mold wafer structure on a stage. The mold wafer structure includes a mold layer and a stack structure positioned on a wafer. The stage includes a center region and an edge region adjacent the center region. Warpage information of the mold wafer structure is obtained. The mold wafer structure is heated by the stage based on the warpage information to reduce a warpage of the mold wafer structure. A temperature of the center region and a temperature of the edge region are different from each other. An operation test is performed on the stack structure.


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