The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 19, 2019

Filed:

May. 12, 2017
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventor:

Rick W. Dudley, San Jose, CA (US);

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01); G01R 31/28 (2006.01); G11C 7/00 (2006.01);
U.S. Cl.
CPC ...
G11C 29/00 (2013.01); G01R 31/2882 (2013.01); G11C 7/00 (2013.01);
Abstract

A method of making measurements in a testing arrangement having a plurality of devices under test is described. The method comprises configuring a device interface board with the plurality of devices under test; running a set of test vectors in a plurality of loops on each device under test of the plurality of devices under test, wherein the set of test vectors is run in parallel on the plurality of devices under test and comprises edge shifted test vectors which are shifted by a predetermined edge shift step during each loop; receiving test result data for the plurality of devices under test; and determining, for each device under test, fail information to identify when the device under test failed based upon a number of edge shift steps. A system for making measurements in a testing arrangement having a plurality of devices under test is also described.


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