The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 19, 2019

Filed:

Mar. 06, 2017
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Jason Villarreal, Los Gatos, CA (US);

Mahesh Sankroj, Secunderabad, IN;

Nikhil A. Dhume, Hyderabad, IN;

Kumar Deepak, San Jose, CA (US);

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/36 (2006.01); G06F 17/50 (2006.01); G06F 11/277 (2006.01); G06F 9/44 (2018.01);
U.S. Cl.
CPC ...
G06F 11/3636 (2013.01); G06F 11/277 (2013.01); G06F 11/3628 (2013.01); G06F 11/3648 (2013.01); G06F 11/3656 (2013.01); G06F 11/3664 (2013.01); G06F 17/5027 (2013.01);
Abstract

An approach for debugging a circuit implementation of a software specification includes translating a high-level language debugging command into a hardware debugging command that specifies the value(s) of a condition in the circuit implementation, and a storage element(s) at which the value(s) of the condition is stored. The hardware debugging command is transmitted to a debug controller circuit that generates a single clock pulse to the circuit implementation. The debug controller circuit reads a value(s) from the storage element(s) specified by the hardware debugging command and determines whether or not the value(s) satisfies the condition. The debug controller circuit generates another single clock pulse in response to the value(s) read from the storage element(s) not satisfying the condition. Generation of pulses of the clock signal is suspended and data indicative of a breakpoint is output in response to the value(s) read from the storage element(s) satisfying the condition.


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