The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 19, 2019

Filed:

Mar. 23, 2016
Applicant:

Fujitsu Limited, Kawasaki-shi, Kanagawa, JP;

Inventors:

Hidefumi Kobayashi, Yokohama, JP;

Satoshi Yazawa, Kawasaki, JP;

Atsushi Igashira, Yokohama, JP;

Wataru Iizuka, Kawasaki, JP;

Motohiro Sakai, Nerima, JP;

Akihito Kobayashi, Kawasaki, JP;

Shinichiro Matsumura, Kawasaki, JP;

Kenji Kobayashi, Kawasaki, JP;

Assignee:

FUJITSU LIMITED, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/32 (2006.01); G06F 12/0804 (2016.01); G06F 12/0868 (2016.01); G06F 12/0871 (2016.01); G06F 1/3234 (2019.01);
U.S. Cl.
CPC ...
G06F 1/3275 (2013.01); G06F 12/0804 (2013.01); G06F 12/0868 (2013.01); G06F 12/0871 (2013.01); G06F 2212/1028 (2013.01); G06F 2212/283 (2013.01); Y02D 10/13 (2018.01);
Abstract

A first control apparatus includes a first memory unit including a local cache, a first power supply that supplies electric power to the first memory unit, and a control unit. The control unit controls a write into a memory device by a write-back method, using the local cache. The control unit mirrors data of the local cache in a mirror cache of a second control apparatus. The control unit determines whether the mirror cache is included in a second memory unit that receives electric power from a second power supply of the second control apparatus, upon detecting an abnormal state of a battery for supplying electric power to the second memory unit in case of power outage of the second power supply. The second memory unit switches write control for the memory device to a write-through method, when the second memory unit includes the mirror cache.


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