The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 19, 2019

Filed:

Jan. 30, 2015
Applicant:

Hewlett-packard Development Company, L.p., Houston, TX (US);

Inventors:

Zhizhang Chen, Corvallis, OR (US);

Mohammed Saad Shaarawi, Corvallis, OR (US);

Roberto A Pugliese, Jr., Tangent, OR (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/52 (2006.01); B41J 2/14 (2006.01); C23C 16/04 (2006.01); C23C 16/455 (2006.01); H01L 21/768 (2006.01); B41J 2/16 (2006.01);
U.S. Cl.
CPC ...
B41J 2/14129 (2013.01); B41J 2/1603 (2013.01); B41J 2/1628 (2013.01); B41J 2/1629 (2013.01); B41J 2/1631 (2013.01); B41J 2/1642 (2013.01); B41J 2/1645 (2013.01); B41J 2/1646 (2013.01); C23C 16/045 (2013.01); C23C 16/45525 (2013.01); H01L 21/76832 (2013.01); H01L 21/76834 (2013.01);
Abstract

In one example, a liquid ejection device. The device includes a first metal layer over a substrate, a dielectric layer over the first metal layer, and an orifice through the dielectric layer to the first metal layer. The device also includes a second metal layer over the dielectric layer and partially filling the orifice to form a via to electrical connect the two metal layers. The via has a depth-to-width ratio of at least 0.4. The device further includes a passivation stack covering the second metal layer including all interior surfaces of the via. The stack includes an ALD-deposited layer formed by atomic layer deposition.


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