The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 12, 2019

Filed:

Jun. 14, 2017
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventor:

Takuro Nishikawa, Tokyo, JP;

Assignee:

Renesas Electronics Corporation, Koutou-ku, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/10 (2006.01); H03M 13/00 (2006.01); H04L 1/00 (2006.01); H03M 13/15 (2006.01); H04B 1/40 (2015.01); H03M 13/09 (2006.01);
U.S. Cl.
CPC ...
H04L 1/0061 (2013.01); H03M 13/091 (2013.01); H03M 13/157 (2013.01); H03M 13/6522 (2013.01); H04B 1/40 (2013.01);
Abstract

Provided is a CRC calculation circuit capable of dealing with various types of generator polynomials with a simple configuration. A CRC calculation circuit () includes a generator polynomial register () configured to store polynomial data, and a plurality of CRC calculation units () connected in series and provided so as to correspond to the number of bits of input data. The CRC calculation units () each include a barrel shifter () configured to shift calculated data by one bit using the input data or output data from a pre-stage CRC calculation unit as the calculated data; an XOR circuit () configured to perform XOR calculation of the shifted data and the polynomial data; and a multiplexer () configured to select, based on the calculated data, the shifted data or calculation result data.


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