The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 12, 2019

Filed:

Mar. 19, 2018
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventors:

Yukitoshi Tsuboi, Tokyo, JP;

Hideo Nagano, Kawasaki, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 13/00 (2006.01); H03M 13/29 (2006.01); G06F 11/10 (2006.01); H03M 13/09 (2006.01); H03M 13/13 (2006.01); H03M 13/19 (2006.01); H03M 13/11 (2006.01); H03M 13/15 (2006.01); H03M 13/37 (2006.01);
U.S. Cl.
CPC ...
H03M 13/2927 (2013.01); G06F 11/1012 (2013.01); G06F 11/1044 (2013.01); G06F 11/1052 (2013.01); H03M 13/095 (2013.01); H03M 13/11 (2013.01); H03M 13/13 (2013.01); H03M 13/19 (2013.01); H03M 13/29 (2013.01); H03M 13/6575 (2013.01); H03M 13/1575 (2013.01); H03M 13/3715 (2013.01);
Abstract

A data processing apparatus includes a memory, a processor which outputs write data when making a write request to the memory, and which inputs read data when making a read request to the memory, a parity generating circuit which generates a parity comprising a plurality of parity bits from the write data, the parity being written with the write data into the memory, and a parity check circuit which is coupled between the memory and the processor, and which detects a presence or absence of an error of one bit or two bits in the read data and the parity read from the memory, wherein the parity generating circuit generates the parity so that at least one of a first write data bit and a second write data bit included in the write data contributes to generation of at least two parity bits.


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