The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 12, 2019

Filed:

Feb. 21, 2018
Applicants:

Kabushiki Kaisha Toshiba, Minato-ku, Tokyo, JP;

Toshiba Electronic Devices & Storage Corporation, Minato-ku, Tokyo, JP;

Inventors:

Atsushi Namai, Kanagawa, JP;

Junichi Todaka, Oita, JP;

Shuji Toda, Kanagawa, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 3/012 (2006.01); H03K 17/687 (2006.01); H03K 3/037 (2006.01); H03K 5/00 (2006.01); H03K 19/0185 (2006.01);
U.S. Cl.
CPC ...
H03K 3/012 (2013.01); H03K 3/037 (2013.01); H03K 17/687 (2013.01); H03K 19/0185 (2013.01); H03K 5/00 (2013.01); H03K 2005/00013 (2013.01);
Abstract

According to one embodiment, a gate control circuit includes a controller, a delay circuit, a power circuit, a boosting circuit, a first transistor, and a control circuit. The controller outputs first and second control signals based on a control signal from outside. The delay circuit delays the first control signal. The power circuit is capable of controlling a power supply voltage to be output based on the delayed first control signal. The boosting circuit is capable of boosting and outputting an input voltage. The first transistor has one end connected to an output node of the boosting circuit, and the other end grounded. The control circuit is capable of controlling a gate voltage of the first transistor based on the second control signal.


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