The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 12, 2019

Filed:

Aug. 08, 2017
Applicant:

Finisar Corporation, Sunnyvale, CA (US);

Inventors:

Luke Graham, Allen, TX (US);

Andy MacInnes, Allen, TX (US);

Assignee:

FINISAR CORPORATION, Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/311 (2006.01); H01S 5/183 (2006.01); H01S 5/042 (2006.01); H01S 5/10 (2006.01); H01S 5/42 (2006.01); H01S 5/20 (2006.01);
U.S. Cl.
CPC ...
H01S 5/18311 (2013.01); H01S 5/0421 (2013.01); H01S 5/0425 (2013.01); H01S 5/1053 (2013.01); H01S 5/18308 (2013.01); H01S 5/18341 (2013.01); H01S 5/18361 (2013.01); H01S 5/18394 (2013.01); H01S 5/2086 (2013.01); H01S 5/42 (2013.01); H01S 5/18322 (2013.01); H01S 5/18358 (2013.01); H01S 5/209 (2013.01); H01S 5/423 (2013.01); H01S 2301/203 (2013.01);
Abstract

An etched planarized VCSEL includes: an active region; a blocking region over the active region, and defining apertures therein; and conductive channel cores in the apertures, wherein the conductive channel cores and blocking region form an isolation region. A method of making the VCSEL includes: forming the active region; forming the blocking region over the active region; etching the apertures in the blocking region; and forming the conductive channel cores in the apertures of the blocking region. Another etched planarized VCSEL includes: an active region; a conductive region over the active region, and defining apertures therein; and blocking cores in the apertures, wherein the blocking cores and conductive region form an isolation region. A method of making the VCSEL includes: forming the active region; forming the conductive region over the active region; etching the apertures in the conductive region; and forming the blocking cores in the apertures of the conductive region.


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