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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10229998 B1

PDFFull Text
Date of Patent:
Mar. 12, 2019

Filed:

Mar. 07, 2018

Semiconductor device and method of manufacturing the same

Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventor:

Tatsuyoshi Mihara, Tokyo, JP;

Assignee:

RENESAS ELECTRONICS CORPORATION, Tokyo, JP;

Attorney:

McGinn I. P. Law Group, PLLC.

Primary Examiner:

Asok K Sarkar

Assistant Examiner:

Grant Withers

Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 29/423 (2006.01); H01L 29/51 (2006.01); H01L 21/3105 (2006.01); H01L 21/762 (2006.01); H01L 21/28 (2006.01); H01L 21/02 (2006.01); H01L 27/11524 (2017.01);
U.S. Cl.
CPC ...
H01L 29/7851 (2013.01); H01L 21/02164 (2013.01); H01L 21/28273 (2013.01); H01L 21/31055 (2013.01); H01L 21/76224 (2013.01); H01L 27/11524 (2013.01); H01L 29/4234 (2013.01); H01L 29/42324 (2013.01); H01L 29/42344 (2013.01); H01L 29/513 (2013.01); H01L 29/66795 (2013.01); H01L 29/7855 (2013.01); H01L 29/7856 (2013.01);
Abstract

Variations in height of a top of an element isolation region, which is embedded in a trench surrounding the periphery of a fin having a channel region of a split-gate MONOS memory, are suppressed to improve reliability of a semiconductor device. An element isolation region embedded in a trench between a plurality of fins, which are part of a semiconductor substrate in a memory cell region and protrude above the semiconductor substrate, is comprised of an insulating film covering the bottom of the trench and a silicon nitride film covering the top of the insulating film.

Find Patent Forward Citations

Mihara, Tatsuyoshi. (2019). Semiconductor device and method of manufacturing the same (U.S. Patent No. 10229998). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10229998

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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