The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 12, 2019

Filed:

Aug. 09, 2016
Applicant:

Seagate Technology Llc, Longmont, CO (US);

Inventors:

Timothy Canepa, Longmont, CO (US);

Stephen Hanna, Longmont, CO (US);

Assignee:

Seagate LLC, Cupertino, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/10 (2006.01); H03M 13/15 (2006.01); G11C 16/22 (2006.01); G11C 29/52 (2006.01); G11C 11/56 (2006.01); G11C 16/14 (2006.01); H03M 13/11 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1072 (2013.01); G11C 11/5628 (2013.01); G11C 11/5635 (2013.01); G11C 16/14 (2013.01); G11C 16/22 (2013.01); G11C 29/52 (2013.01); H03M 13/154 (2013.01); G11C 2211/5641 (2013.01); H03M 13/11 (2013.01);
Abstract

Methods and structure for preventing lower page corruption in flash memory. One embodiment is a flash storage device that includes Multi-Level Cell (MLC) flash memory, Single-Level Cell (SLC) flash memory, and a controller coupled to the MLC flash memory and the SLC flash memory. The controller is configured to program host data to a lower page of the MLC flash memory, to generate an erasure code for the host data, and to store the erasure code in the SLC flash memory. The controller is also configured to detect an interrupted write operation to an upper page linked to the lower page, to retrieve the erasure code from the SLC flash memory, and to correct the host data of the lower page of the MLC flash memory using the erasure code.


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