The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 12, 2019

Filed:

Dec. 06, 2016
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventor:

Masami Nakajima, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 9/48 (2006.01); G06F 12/0868 (2016.01); G06F 12/0897 (2016.01);
U.S. Cl.
CPC ...
G06F 3/0659 (2013.01); G06F 3/0625 (2013.01); G06F 3/0685 (2013.01); G06F 9/4812 (2013.01); G06F 12/0868 (2013.01); G06F 12/0897 (2013.01); G06F 2212/1021 (2013.01); G06F 2212/202 (2013.01); Y02D 10/13 (2018.01);
Abstract

A semiconductor device according to the present invention includes: a memory unit provided with a lower-order memory and a cache memory to cache a data stored in the lower-order memory; a power control circuit to control power supply of the lower-order memory; and a bus master to access the data stored in the memory unit after locking the bus. When the power supply of the lower-order memory is cut off at the time of occurrence of a mishit of the cache memory, the power control circuit restores the power supply of the lower-order memory, and the memory unit outputs a response to the access to the bus master. The bus master once releases the lock of the bus according to the response from the memory unit and reexecutes the access with the bus locked, after the restoration of the power supply of the lower-order memory is completed.


Find Patent Forward Citations

Loading…