The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 12, 2019

Filed:

Aug. 17, 2015
Applicants:

Boe Technology Group Co., Ltd., Beijing, CN;

Beijing Boe Optoelectronics Technology Co., Ltd., Beijing, CN;

Inventors:

Chong Liu, Beijing, CN;

Wei Wang, Beijing, CN;

Haisheng Zhao, Beijing, CN;

Zhilong Peng, Beijing, CN;

Zhilian Xiao, Beijing, CN;

Huanping Liu, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02F 1/1362 (2006.01); G02F 1/1343 (2006.01); G02F 1/1368 (2006.01);
U.S. Cl.
CPC ...
G02F 1/136286 (2013.01); G02F 1/1368 (2013.01); G02F 1/13439 (2013.01); G02F 1/134309 (2013.01); G02F 1/134336 (2013.01); G02F 2201/121 (2013.01); G02F 2201/123 (2013.01);
Abstract

The present disclosure discloses an array substrate, a display panel and a display device. The array substrate includes gate regions, gate lines, data lines, pixel electrodes and common electrode lines. The common electrode lines and the gate lines have the same extension direction, the pixel electrodes are located in regions defined by adjacent gate lines and adjacent data lines, the gate lines traverse the gate regions in the extension direction that are located in the same row as the gate lines, and the pixel electrodes have a gap from the gate lines at ends thereof closer to the gate lines. As such, a portion of the gate region that extends to the pixel region has a reduced area and hence a reduced edge length. This way, during the cleaning of the active layer after formation, less active layer metal may remain at the edges of the gate region. Thereby, the array substrate fabrication process is improved, and a product yield rate of the array substrate is increased.


Find Patent Forward Citations

Loading…