The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 05, 2019

Filed:

Sep. 19, 2016
Applicant:

Invisage Technologies, Inc., Menlo Park, CA (US);

Inventors:

Hui Tian, Cupertino, CA (US);

Pierre Henri Rene Della Nave, Mountain View, CA (US);

Assignee:

INVISAGE TECHNOLOGIES, INC., Newark, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04N 5/378 (2011.01); H04N 5/376 (2011.01); H04N 5/225 (2006.01); H04N 5/369 (2011.01); H04N 9/04 (2006.01); H04N 5/3745 (2011.01); H04N 5/361 (2011.01); H04N 5/357 (2011.01); H04N 5/363 (2011.01);
U.S. Cl.
CPC ...
H04N 5/378 (2013.01); H04N 5/2253 (2013.01); H04N 5/3575 (2013.01); H04N 5/361 (2013.01); H04N 5/363 (2013.01); H04N 5/3698 (2013.01); H04N 5/3745 (2013.01); H04N 5/3765 (2013.01); H04N 9/045 (2013.01); H04N 2209/047 (2013.01);
Abstract

Image sensors and methods of using image sensors are disclosed. In an embodiment, the image sensor includes pixel regions having optically sensitive material (OSM). A bias voltage is provided to the OSM via a bias electrode for each pixel region. A pixel circuit (PC) for each pixel region includes a read out circuit and a charge store (CS) coupled to the OSM of the respective pixel region. The PC resets voltage on the CS to a reset voltage during a reset period, integrates charge from the OSM to the CS during an integration period, and reads out a signal from the CS during a read out period. The PC includes a reference voltage node coupled to the CS during the reset period and the read out circuit during the read out period, a reference voltage is applied to the reference voltage node and is varied during operation of the PC.


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