The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 05, 2019

Filed:

Jan. 29, 2018
Applicant:

Fujitsu Limited, Kawasaki-shi, Kanagawa, JP;

Inventors:

Wahid Rahman, Kanata, CA;

Ali Sheikholeslami, Toronto, CA;

Takayuki Shibasaki, Kawasaki, JP;

Hirotaka Tamura, Yokohama, JP;

Assignee:

FUJITSU LIMITED, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/08 (2006.01); H04L 7/00 (2006.01); H03L 7/085 (2006.01); H03L 7/087 (2006.01); H03L 7/099 (2006.01); H04L 7/033 (2006.01);
U.S. Cl.
CPC ...
H04L 7/0037 (2013.01); H03L 7/085 (2013.01); H03L 7/0807 (2013.01); H03L 7/087 (2013.01); H03L 7/099 (2013.01); H04L 7/0079 (2013.01); H04L 7/033 (2013.01);
Abstract

A CDR circuit includes: a comparison circuit that receives data signal on which a first clock signal is superimposed, and outputs a comparison result obtained by comparing the data signal with three different threshold values at a timing synchronized with a second clock signal; a data pattern detection circuit that detects an occurrence of a data pattern, based on the comparison result; a frequency detection circuit that outputs, when an occurrence of the data pattern is detected, a detection result indicating whether a second frequency of the second clock signal is higher than a first frequency of the first clock signal; an adjustment circuit that outputs, based on the detection result, an adjustment signal for adjusting a phase of the second clock signal and the second frequency; and an oscillator circuit that outputs the second clock signal with the phase and the second frequency adjusted, based on the adjustment signal.


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