The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 05, 2019
Filed:
Oct. 30, 2014
Applicant:
Hewlett-packard Development Company, L.p., Houston, TX (US);
Inventors:
Assignee:
HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P., Spring, TX (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/18 (2006.01); H03K 19/173 (2006.01); H03K 3/45 (2006.01); H03K 19/0944 (2006.01); G11C 13/00 (2006.01);
U.S. Cl.
CPC ...
H03K 19/18 (2013.01); H03K 3/45 (2013.01); H03K 19/0944 (2013.01); H03K 19/173 (2013.01); G11C 13/0002 (2013.01);
Abstract
A device having ratioed logic with a high impedance load is described. The device includes a pull-down network coupled between a first voltage and an output. The device also includes a high impedance load coupled between a second voltage and the output. The high impedance load being smaller than a transistor of the pull-down network.
Ge, Ning. (2019). Ratioed logic with a high impedance load (U.S. Patent No. 10224935). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10224935
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile