The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 05, 2019

Filed:

Oct. 12, 2016
Applicant:

Shenzhen China Star Optoelectronics Technology Co., Ltd., Guangdong, CN;

Inventors:

Zhichao Zhou, Guangdong, CN;

Yulien Chou, Guangdong, CN;

Yue Wu, Guangdong, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/77 (2017.01); H01L 27/12 (2006.01); H01L 29/417 (2006.01); G02F 1/1368 (2006.01);
U.S. Cl.
CPC ...
H01L 29/41733 (2013.01); H01L 21/77 (2013.01); H01L 27/12 (2013.01); H01L 27/127 (2013.01); H01L 27/1225 (2013.01); H01L 29/41741 (2013.01); G02F 1/1368 (2013.01);
Abstract

A TFT array substrate includes a glass substrate, a buffer layer on the glass substrate, a source electrode, a passivation layer on the buffer layer, a gate electrode on the passivation layer, a gate insulating layer on the passivation layer and the gate electrode, an active layer, and a pixel electrode on the gate insulating layer and the active layer. A first source hole is formed in the buffer layer. The source electrode is disposed in the first source hole. A second source hole is formed in the passivation layer and over the first source hole. The source electrode extends into the second source hole. An active layer mounting hole is formed in the gate insulating layer and over the second source hole. The active layer is in the active layer mounting hole.


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