The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 05, 2019

Filed:

Jun. 06, 2017
Applicant:

Osram Opto Semiconductors Gmbh, Regensburg, DE;

Inventors:

Ewald Karl Michael Günther, Regenstauf, DE;

Andreas Plöβl, Regensburg, DE;

Heribert Zull, Regensburg, DE;

Thomas Veit, Mintraching, DE;

Mathias Kämpf, Burglengenfeld, DE;

Jens Dennemarck, Regensburg, DE;

Bernd Böhm, Obertraubling, DE;

Korbinian Perzlmaier, Regensburg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/60 (2006.01); H01L 25/16 (2006.01); H01L 27/02 (2006.01); H01L 27/14 (2006.01); H01L 27/15 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 33/00 (2010.01); H01L 33/38 (2010.01); H01L 33/64 (2010.01);
U.S. Cl.
CPC ...
H01L 29/0607 (2013.01); H01L 25/167 (2013.01); H01L 29/66128 (2013.01); H01L 23/60 (2013.01); H01L 27/0248 (2013.01); H01L 27/14 (2013.01); H01L 27/15 (2013.01); H01L 33/0079 (2013.01); H01L 33/382 (2013.01); H01L 33/641 (2013.01); H01L 2224/48247 (2013.01); H01L 2224/49107 (2013.01); H01L 2224/73265 (2013.01);
Abstract

A method of producing a plurality of semiconductor chips includes a) providing a carrier substrate having a first major face and a second major face opposite the first major face; b) forming a diode structure between the first major face and the second major face, the diode structure electrically insulating the first major face from the second major face at least with regard to one polarity of an electrical voltage; c) arranging a semiconductor layer sequence on the first major face of the carrier substrate; and d) singulating the carrier substrate with the semiconductor layer sequence into a plurality of semiconductor chips.


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