The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 05, 2019

Filed:

Jan. 29, 2015
Applicant:

Hewlett-packard Development Company, L.p., Houston, TX (US);

Inventors:

Wai Mun Wong, Singapore, SG;

Leong Yap Chia, Singapore, SG;

Ning Ge, Palo Alto, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/49 (2006.01); H01L 27/11521 (2017.01); H01L 27/1156 (2017.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11521 (2013.01); G11C 16/0433 (2013.01); H01L 27/1156 (2013.01);
Abstract

The present subject matter relates to an integrated circuit comprising an erasable programmable read only memory (EPROM) array having a plurality of EPROM cells disposed in rows and columns, wherein one or more EPROM cells located at predetermined positions in the EPROM array are selectively dischargeable. The one or more EPROM cells comprise a EPROM transistor having a first conductive layer to store electrons upon the EPROM transistor being programmed and a control metal oxide semiconductor field-effect transistor (MOSFET) electrically connected to the first conductive layer to provide an electron leakage path to dissipate the electrons stored in the first conductive layer in a predetermined leak time period.


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