The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 05, 2019

Filed:

May. 18, 2016
Applicant:

Sharp Kabushiki Kaisha, Sakai, Osaka, JP;

Inventors:

Masaki Nakayama, Sakai, JP;

Motoji Shiota, Sakai, JP;

Takashi Matsui, Sakai, JP;

Yasuhiko Tanaka, Sakai, JP;

Hiroki Miyazaki, Sakai, JP;

Seiji Muraoka, Sakai, JP;

Assignee:

SHARP KABUSHIKI KAISHA, Sakai, Osaka, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 27/12 (2006.01); G02F 1/1345 (2006.01);
U.S. Cl.
CPC ...
H01L 24/73 (2013.01); G02F 1/13454 (2013.01); G02F 1/13458 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 27/124 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/32227 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/8319 (2013.01); H01L 2924/1426 (2013.01);
Abstract

In order to inhibit defective connection between a bump of a semiconductor chip and an electrode pad of a substrate, a semiconductor device includes a substrate provided on a surface with a plurality of electrode pads, a semiconductor chipprovided on a surface with a plurality of bumpssubstantially equal in size, and an anisotropic conductive filminterposed between the plurality of bumpsand the plurality of electrode padsand electrically connecting each of the bumpsand corresponding one of the electrode pads. The plurality of electrode padsincludes a plurality of first electrode padsA positioned closest to an endof the semiconductor chip, and a plurality of second electrode padsB positioned inside the plurality of first electrode padsA on the semiconductor chip. Each of the second electrode padsB is larger in area than each of the first electrode padsA.


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