The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 05, 2019

Filed:

Sep. 22, 2017
Applicant:

Imec Vzw, Leuven, BE;

Inventors:

Bernardette Kunert, Wilsele, BE;

Niamh Waldron, Heverlee, BE;

Weiming Guo, Heverlee, BE;

Assignee:

IMEC vzw, Leuven, BE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8258 (2006.01); H01L 21/8234 (2006.01); H01L 21/8252 (2006.01); H01L 21/84 (2006.01); H01L 27/12 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 21/8258 (2013.01); H01L 21/8252 (2013.01); H01L 21/823487 (2013.01); H01L 21/84 (2013.01); H01L 21/845 (2013.01); H01L 27/1203 (2013.01); H01L 29/66742 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 29/78642 (2013.01); H01L 29/42392 (2013.01); H01L 29/66522 (2013.01); H01L 29/66666 (2013.01); H01L 29/7827 (2013.01);
Abstract

The disclosed technology generally relates to semiconductor devices, and more specifically to a semiconductor device having a high aspect ratio channel layer. In one aspect, semiconductor device includes a semiconductor substrate having formed thereon a dielectric isolation layer having an opening formed therethrough. The semiconductor device additionally includes a filling isolation structure having a portion formed in the opening and a portion protruding above the dielectric isolation layer, wherein the filling isolation structure comprises a dielectric filling layer. The semiconductor device additionally includes a dielectric layer formed on the dielectric isolation layer, wherein the dielectric layer and the dielectric filling layer have top surfaces that are substantially co-planar to form a common top surface. The semiconductor device further includes a first vertical channel layer laterally interposed between and in contact with the dielectric layer and the dielectric filling layer at a first side of the dielectric filling layer, wherein the first vertical channel layer extends above the common top surface.


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